 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| sames FEATURES s Generates PBX supervisory tones in PCM format s s s s SA9401 UNIVERSAL PABX TONE GENERATOR Each of these tone streams selectable from 16 tone blocks Seperate Intrude Tone for each program Choice of clock frequencies Watchdog facility Low power CMOS technology Integrated time slot allocation circuitry No noticeable level changes in tones Frame synch. signal source (internal/ external) selectable Eight tone programs Eight independent PCM tone streams within each program s s s s s s PROGRAMMABLE FEATURES s Tone samples s s s s s s Intrude tone frequency Intrude tone cadence "silence sample" value Tone Cadence timing Tone to time-slot mapping Size of tone blocks DESCRIPTION The SA9401 operates in conjunction with a standard EPROM to generate the system tone plans for the PABX systems of most major countries. The high level of programmability allows the SA9401 to satisfy a wide variety of tone plans. Furthermore by providing three inputs to select between one of eight tone programs during initialisation, the device effectively facilitates the design of a universally programmable "PABX Processor Card". Because the tone program inputs are latched at the start of each PCM frame the SA9401 minimises the possibility of glitches. The SA9401 can also generate the PCM Frame synchronising reference signal if required. 4092 PDS039-SA9401-001 REV. C 07-05-96 SA9401 A7 MRST D0 D1 D2 V CC D3 D4 D5 D6 D7 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 CLK_SEL A0 A1 A2 A3 GND A4 A5 A6 PCMFSC CLKIN 40 41 42 43 44 1 2 3 4 5 6 SA9401 23 22 21 20 19 18 TEST FS1 A8 A9 A11 GND A10 A12 A13 PS2 WD_INT 7 8 9 10 11 12 13 14 15 16 17 DR-00603 Package : PLCC - 44 PIN DESCRIPTION Pin No 1, 23 12, 34 27 6 8 10 5 11 13 15 41, 42, 43, 44, 2, 3, 4, 39, 26, 25, 22, 24, 21, 20 I/0 I I I I O O O O O O O Designation GND VCC FS1 CLKIN 2MCLK 8KFS PCMFSC INTRFRQ INTRCAD PCM_OUT A0..A13 2 sames CLKDIV2 2MCLK PS0 8KFS INTRFRQ VCC INTRCAD PS1 PCM_OUT WD_RST WD_EN Description Supply Ground +5V Power Supply Frame Synchronisation (active low) Master clock input (either 8192kHz or 2048 Khz dependent on logic level of "CLK _SEL") 2048 kHz clock derived internally from CLKIN 8 kHz Frame Synchronisation output. 8 kHz Auxilliary Frame Synchronisation Output Square Wave Intrude Tone Intrude Tone Cadence Signal Tri-state PCM Highway tone output EPROM Address Lines SA9401 PIN DESCRIPTION (Continued) Pin No 37, 36, 35, 33, 32, 31, 30, 29 9, 14, 19 7 40 I/0 I I O I Designation D0..D7 PS0, PS1, PS2 CLKDIV2 CLK_SEL Description EPROM Data Lines Program Select Inputs for Selecting between 1 of 8 tone plans CLKIN divided by 2 output (i.e. 4096 kHz or 1024 kHz depending on CLK_SEL input) Selects between CKLIN of 8192 or 2048 kHz and Synchronisation source. 0 = 8192kHz/Internal 1 = 2048kHz/External Used for IC testing purpose. Tied Low during normal operation. Asynchronous Reset Pin. Resets all Internal Flip Flops (active low) Watchdog reset input (Rising-edge triggered) Tied high if unused Watchdog enable input (active low) Tied high if unused Watchdog output (active low, tri-state) 28 38 16 17 18 I I I I O TEST MRST WD_RST WD_EN WD_INT BLOCK DIAGRAM CLKDIV2 /MRST CLK_SEL CLKIN CLOCK GENERATOR 2MCLK 8KFS PCMFSC WD_RST WDENB D[7 : 0] WATCHDOG TIMER WD_INT INTRUDE TONE GENERATOR INTRFRQ /FS1 CADENCE TIMER INTRCAD PS[2 : 0] EPROM INTERFACE A[13 : 0] TEST PCM INTERFACE SA9401 DR-01085 PCM_OU sames 3 SA9401 FUNCTIONAL DESCRIPTION The design of the SA9401 has been based on the assumption that any supervisory tone used in a PABX (e.g. Dial tone or Busy Tone etc) can be described by a small set of simple parameters and that the tones will be injected into a standard PCM 30 (2048kHz) backplane in either A-law or -law format. In the SA9401 a tone is created by repeating a fundamental waveform (or one of two waveforms) which would typically be one cycle of a sinewave or alternatively may be several cycles of a higher frequency signal (say 400 to 1000Hz) modulated by a lower frequency signal. This Tone may then be interrupted ("Cadenced") so that the tone is effectively switched on and off. The waveform shape, number of samples per cycle and the cadence can all be set by the system designer in accordance with the related National Standards. Once a set of tones have been described they may then be injected into the PCM backplane. The time slot associated with each tone can be set by the system designer. The SA9401 accommodates up to 9 different Tones to form a Tone Plan making ample allowance for Ring, Dial, Busy, Intrude and other Tones. The set of data describing one Tone Plan (waveforms, cadence timings, timeslots etc) is referred to as a Program and is stored in an external EPROM which is addressed directly by the SA9401. Up to eight Tone Plans may be stored and selected at will to accommodate products for multi-national markets. ARCHITECTURE The architecture of the SA9401 consists of 6 functional blocks each of which is described in detail in the following sections. Refer also to the block diagram. Clock Generator The clock generator circuit derives all the timing for the ic from either a 2048kHz or a 8192kHz clock. The desired Clock is selected by the state of the CLK_SEL pin (1 for 2048kHz and 0 for 8192kHz). The CLK_SEL pin also determines the function of the Frame Sync pin. If CLK_SEL is low then Internal synchronisation is assumed and FS1 should be tied high. If CLK_SEL is high then an external Frame Synchronisation source must be connected to /FS1. The Clock Generator comprises 5 functional blocks. A divide-by-4 counter is enabled only if a 8192kHz clock is selected so that all internal timing is based on 2048kHz. The Time Slot Counter keeps track of the Time Slots (0 to 31) in the PCM Frame while the bit position (0 to 7) in each time-slot is tracked by the Bit Position Counter. PCM frame synchronisation signals are controlled by the Frame Generator. Long cadence intervals are accommodated by the Five-ms-Timebase which delivers a 200Hz signal which clocks the Cadence Timers. 4 sames SA9401 Intrude Tone Generator This module generates a square wave output based on the master clock of 2048kHz. The Intrude Tone frequency is determined by the contents of the 16-bit Intrude Tone Register (INTR_LO and INTR_HI) according to the formula:fint = 2048kHz/(2*(n+1)) where n is the content of the INTR register. The range of values in the register (from 0 to 65535) give Intrude tones in the range 15.625Hz to 1024kHz. Cadence Timer In any given Tone Plan the SA9401 assumes that any or all of the 9 (8 PCM tone streams and one squarewave Intrude Tone) tones are required to have their own independently defined cadence. A typical cadence is illustrated in FIGURE 1 above. Each tone is assumed to comprise up to 4 cadence periods which repeat cyclically. The duration of each period is controlled by the Cadence Timers which in turn comprise 10bit Counters. These timers are clocked by the five_ms_timebase generated by the Clock Generator so that intervals of up to 5.12 seconds can be defined with a resolution of 5ms. (10 bits => 1023: 1023*5ms = 5115ms) ON OFF ON OFF TONE_n_A CADO_n DR-01086 CAD1_n TONE_n_B CAD2_n CAD3_n FIGURE 1: TONE CADENCING The Cadence Controller controls the loading of the 10-bit counter and the sequencing of the Cadence Position Counter. The duration of each period of the tone is denoted by the parameter:CADm_n_LO = Period m, Tone stream n low-order 8 bits and CADm_n_HI = Period m, Tone stream n high-order 2 bits where 0 m 3 and 0 n 8 (8 = Intrude Tone) The Cadence Position Counter keeps track of the period being generated and during period 0 the SA9401 generates a tone based on one Tone Block (A) while during the period 2 (if used) the samples from another Block (B) are used. During periods 1 and 3 the silence sample is transmitted. This feature allows the sound of the tone to be altered along with the cadence. A continuous tone is created by loading values of 1(or any non-zero value),0,0,0 into the registers CAD0_n to CAD3_n respectively. The zero value is interpreted by the SA9401 as an instruction to ignore the period and to process the next one. With the register contents shown the Cadence Controller continuously processes the first (ON) period. 5 sames SA9401 EPROM Interface The EPROM Interface controls all aspects of the transfer of program and tone data to the SA9401. This module comprises seven distinct functions. The Program Select Register reflects the settings on pins PS2 - PS0 which are latched into the register at the start of every frame. The mapping of the pin settings to the selected program is by a simple binary code (PS2 = msb). The Cycle Register is loaded with a 9-bit value (CYCLE) indicating the number of samples in a Tone Block (or basic waveform). It is assumed that all basic waveforms in a single Tone Plan will have a common size. Successive samples in a Tone Block are addressed by the 9-bit Sample Counter which cycles through from zero to Cycle-1. The current value of this register and the contents of the Cycle Register are fed to a Comparator which resets the counter after it reaches the terminal value of Cycle-1. The required Tone Block (or waveform) is addressed by the Tone Block Register. The content of the register is a function of the Program Select and Cadence Controller. As previously described, Tone Plans are defined in terms of a basic waveform (Tone Block) and a Program of descriptive parameters which together are stored in an external EPROM. Consequently a Data Fetch from the EPROM may retrieve either a Program Instruction or a Tone Sample. In either case the Address Multiplexer constructs the address according to the following table. ADDRESS LINE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Program Instruction Fetch 1 0 0 0 PSEL2 PSEL1 PSEL0 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Tone Sample Fetch 0 TONE_BLOCK.3 TONE_BLOCK.2 TONE_BLOCK.1 TONE_BLOCK.0 SAMPLE_COUNT.8 SAMPLE_COUNT.7 SAMPLE_COUNT.6 SAMPLE_COUNT.5 SAMPLE_COUNT.4 SAMPLE_COUNT.3 SAMPLE_COUNT.2 SAMPLE_COUNT.1 SAMPLE_COUNT.0 The details of the Address mapping will be described later in the External Data Storage section 6 sames SA9401 PCM Interface The PCM Interface controls all aspects of the transfer of PCM signals onto the PCM highway. Eight-bit Tone Registers store the PCM tone samples and are updated once per PCM frame. Before a PCM word is transmitted to the PCM highway the Tone Selector determines whether or not the Cadence controller requires an OFF period. If so then a specific PCM word for Silence (held in the Silence Register) is substituted for the tone sample. The actual transfer of the tone (or silence) samples to the PCM highway is the function of the Injection Controller. Time Slot Registers indicate to which PCM time-slot the sample is to be injected. These registers (one for each tone stream) comprise 5 address bits and one (high-order) enabling bit. A Comparator checks if the Time Slot Register contents match the current PCM time-slot and if so feeds the Tone Sample (or Silence Sample) into the Parallel In Serial Out module and the required sample is clocked out via the PCM_OUT pin. The PCM_OUT pin is enabled only when samples are being clocked out (ie when the 5 least significant bits of the Time Slot Register matches the current PCM Time Slot and the Time Slot Register MSB is Low) and is held in a tri-state condition at all other times. Watchdog Timer The watchdog timer performs a function completely independently of the Universal Tone Generator. Its operation is described below. The watchdog timer comprises three I/O pins, viz; WD_EN - an active low input which enables/disables the watchdog. WD_RST - a rising edge triggered input which resets the watchdog timer and prevents the output from resetting the microprocessor. WD_INT - an active low tri-state output which when active, resets a microprocessor. The watchdog timer operates as follows: For the watchdog timer to operate, the WD_EN pin must be held low (i.e. active). With the WD_EN pin held high, the WD_INT output remains tri-stated. The delay between WD_EN going active and a WD_INT output is 2 seconds. The timer is reset every time a rising edge is detected on the WD_RST pin. The minimum pulse width of the WD_RST input is two CLKIN periods. The WD_INT output comprises an active low pulse of 5 milliseconds followed by a tri-state period of 1995 milliseconds (assuming no valid WD_RST pulse is detected within 2 seconds of the previous WD_RST pulse). The timing diagram for the Watchdog Timer is given in Figure 2. Note that although the timebase for the Watchdog Timer is always 2048kHz, the WD-EN and WD-RST inputs are strobed at the external clock rate. 7 sames SA9401 FIGURE 2 EXTERNAL DATA STORAGE This section describes in detail the names and definition of the parameters which define the Tone Plan for a PABX. Values for these parameters are selected by the system designer in accordance with the relevant standards and are saved in an external EPROM to be addressed by the SA9401. Reference can be made to the diagram of fig. 3 which defines the memory map of the EPROM. 23FFH Program 7 2380H 237FH Program 6 2300H 22FFH Program 5 2280H 227FH Program 4 2200H 21FFH Program 3 2180H 217FH Program 2 2100H 20FFH Program 1 2030H 207FH Program 0 2000H + 6DH + 6CH + 6BH + 6AH + 6E-7FH +66-7DH +5A-65H + 4E-59H + 42-4DH + 36-41H + 2A-35H + 1E-29H + 12-1DH + 06-11H +00-05H Not Used Intrude Tone Tone Stream 7 6 5 4 3 1 0 Initialisation + 11H + 69H + 68H + 67H + 66H CAD3_8_HI CAD3_8_LO CAD2_8_HI CAD2_8_LO CAD1_8_HI CAD1_8_LO CAD1_8_HI CAD0_8_LO Program p BASE ADDR = 2000 + p*80H TIME_SLOT_n CAD3_n_HI CAD3_n_LO CAD2_n_HI CAD2_n_LO CAD1_n_HI CAD1_n_LO CAD0_n_HI CAD0_n-LO Unused TONE_BLOCK_n-B TONE_BLOCK_n_A Tone stream n 3FFFH 2 + 10H + 0FH + OEH + ODH + OCH + OBH + 0AH + 09H + 08H + 07H + 06H Unused 2400H 23FFH Programs 2000H 1FFFH 1E00-1FFFH Tone Blk F 1C00-1DFFH 1A00-1BFFH 1800-19FFH E D C B A 9 8 7 6 5 4 3 2 1 0 BASE ADDR = 2000 + p * 80H BASE + 1 FFH Unused 1200-13FFH 1000-11FFH Tone Block b Tone Blocks 0000H 1600-17FFH 1400-15FFH BASE + CYCLE BASE + CYCLE - 1 PCM Samples BASE ADDR (b * 0200H) 0E00-0FFFH 0C00-0DFFH BASE = 2000+ P*80+ n*CH + 05H + 04H + 03H + 02H + 01H + 00H INTR_HI INTR_LO SILENCE CYCLE_HI CYCLE_LO Unused 16kbyte EPROM 0A00-0BFFH 0800-09FFH 0600-07FFH 0400-05FFH 0200-03FFH 0000-01FFH 8 sames SA9401 The EPROM contents can be divided into two distinct sections. The smaller section contains eight Programs, each of which would typically describe all the tones required by a PABX used in a single country. Thus a single EPROM can be programmed to cover up to eight different countries requirements. The larger part of the EPROM is occupied by the sets of PCM samples which make up the basic waveforms to be used by the SA9401 in creating the familiar supervisory tones. Each of 16 waveforms can contain up to 511 samples of A or law samples. WD_EN WD_INT 5ms 2000ms WD_RST DR-01119 2000ms 5ms 2000ms 244ms 2000ms Program A single Program comprises one set of Initialisation Data, 8 PCM Tone Streams with the associated Cadence, Timeslot and Waveform and one Intrude Tone with its associated Cadence. Each individual variable is described below. Initialisation The Initialisation data describes parameters common to all the tones in a given plan. Variable CYCLE SILENCE INTR bits 9 8 16 Composition Description CYCLE_HI Identifies the number of samples in the CYCLE_LO Tone Block. (from 1 to 511) The Silence sample to be used during cadence period 1 and 3. INTR_HI The divisor used to generate the INTR_LO Intrude Tone Frequency. PCM Tone Stream The Tone Stream Data describes the characteristics of a specific PCM Tone. Note that the length of the Cadence periods are defined in multiples of 5ms. sames 9 SA9401 Variable CAD0_8 Bits 10 Composition CAD0_8_HI CAD0_8_LO CAD1_8_HI CAD1_8_LO CAD2_8_HI CAD2_8_LO CAD3_8_HI CAD3_8_LO Description Length of the first (ON) cadence period. Length of the second (OFF) cadence period. Length of the third (ON) cadence period. Length of the Fourth (OFF) cadence period. CAD1_8 10 CAD2_8 10 CAD3_8 10 Intrude Tone This data describes the characteristics of the Intrude Tone Cadence output on pin INTRCAD of the SA9401. Variable TONE_BLOCK _n_A TONE_BLOCK _n_B CAD0_n Bits 4 Composition Description Number of the Tone Block to be used in the first Cadence period. Number of the Tone Block to be used in the third Cadence period. CAD0_n_HI CAD0_n_LO CAD1_n_HI CAD1_n_LO CAD2_n_HI CAD2_n_LO CAD3_n_HI CAD3_n_LO Length of the first (ON) cadence period. 4 10 CAD1_n 10 Length of the second (OFF) cadence period. Length of the third (ON) cadence period. CAD2_n 10 CAD3_n 10 Length of the Fourth (OFF) cadence period. The number of the Time Slot into which the tone is to be injected. Valid only if MSB is Low. TIME_SLOT_ n 6 10 sames SA9401 Tone Waveform The frequency content of any desired tone is defined by taking one cycle of the tone (which may be a simple or complex waveform) and calculating the series of PCM samples which would result if that tone were passed through a CODEC. The definition of a waveform is perhaps best illustrated by way of an example. Consider the case of a PTT dial tone which is a signal of 400Hz modulated at 33.33Hz as illustrated in fig. 4 below. The first step is to identify the lowest frequency in the composite signal, in this case 33.33Hz. Next the designer should confirm that one cycle of the lower frequency component of the signal will contain an integer number of cycles of the higher frequency component. In the example there are exactly 12 cycles of the 400Hz signal contained within the one cycle of the modulating signal. If this is not the case then the tone sample should be designed to contain two or more cycles of the lower frequency tone, subject to the maximum of 512 samples. It is also typical to take a block of the signal which starts and ends at two similar zero crossing points. Although any arbitrary point in the waveform may be used a careless choice may lead to the introduction of undesirable harmonics. Having chosen a suitable tone sample it is possible to determine the value for CYCLE as the size of the tone block is simply the number of samples (at 8k samples per second) which fall into the waveform chosen. In the example CYCLE = 240 samples = F0H. 1 / 33.3Hz = 30ms DR-01087 1 / 400Hz = 2.5ms 30ms @ 8k SAMPLES / sec = 240 SAMPLES = CYCLE FIGURE 4 400Hz Tone modulated at 33.33Hz. sames NOTE THAT SIGNAL AND ENVELOPE START ON ZERO CROSSING POINT 11 SA9401 Finally the system designer should calculate the PCM sample value for each of the 240 samples in the block. The PCM values used may of course be calculated according to either A or -law and adjusted to suit the required amplitude. Up to 16 Tone Blocks may be defined each with a maximum of 511 samples. Tone Blocks are stored in the EPROM starting at address b * 0200H where b is the number of the block from 0 to 15 (decimal). APPLICATION INFORMATION To simplify the translation of Tone Plan requirements to EPROM data SAMES offer a Support Software pack. This elegant package will guide the designer through the definition of Tone Plans and translate the requirements into a hex source file ready for most commonly used PROM programmers. For more details contact your nearest SAMES representative. AC PARAMETERS TA = 0C to + 70C, VCC = 5V 5%. Load Cap<= 50pf AC PARAMETERS Propagation delay of outputs synchronous to CLKIN (i.e. 2MCLK, CLKDIV2, and WD_INT) relative to CLKIN rising clock edge Propagation delay of outputs synchronous to 2MCLK (i.e. INTRFRQ, 8KFS, PCMFSC, INTRCAD, PCM_OUT, A0..A13 Delay to float of PCM_OUT AFTER LAST BIT OF TIME-SLOT OUTPUT Delay to float of WD_INT after going inactive D0..D7 setup to 2MCLK rising edge D0..D7 hold after 2MCLK rising edge Absolute Maximum Ratings* Parameters Supply Voltage Voltage on any I/O pin Current on any I/O pin Storage Temperature Package Power Dissipation SYM Pd8M MIN TYP 0 20 MAX UNITS 40 ns Pd2M 0 20 40 ns Pf po PfWD SdD HdD Min -0.3 -0.3 -10 -55 0 0 100 0 30 30 60 60 ns ns ns ns Symbol VDD VI/V 0 II/I0 TSIG PD Max 7.0 VDD +0.3 +10 +125 1000 Unit V V mA C mW * Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This a stress rating only. Functional operation of the device at these or any other condition above those inidcated in the operational sections of this specification, is not implied. Exposure to Absolute Maximum Ratings for extended periods may effect device reliability. 12 sames SA9401 DC Characteristics TA = 0 to 70C; VDD = 5V 5%; VSS = OV Limit Values Min. Max. 1.0 4.0 4.5 2.273 ILI I LO -10 -10 10 10 VDD+0.3 0.5 Parameter L-input voltage H-input voltage L-input voltage H-output voltage Operating Frequency Input leakage current Output leakage current Symbol VIL VIH VOL VOH Unit V V V V MHz A A Test Conditions VDD = 5V VDD = 5V IOL = 0.1mA IOH = 0.1mA VDD = 5V 0V < VIN < VDD 0V < VOUT < VDD Characteristics TA = 25C; VDD = 5V 5%; VSS = OV Parameter Input capacitance Output capacitance I/O Symbol C IN C OUT CIO Limit Values Min. Max. 10 15 20 Unit pF pF pF sames 13 SA9401 Figure 5 - Timing Diagram (CLK_SEL=0, CLKIN=8MHz, 6 3 5 TIME-SLOT 0 6 TIME-SLOT 31 TIME-SLOT 0 7 1 2 7 4 7 0 1 6 2 0 3 0 3 4 1 4 5 2 6 5 7 0 7 0 14 PCM OUTPUT STRUCTURE 7 1 3 5 7 0 6 4 2 0 5 4 3 2 1 0 7 6 TIME-SLOT 31 TIME-SLOT 0 CLKIN CLKDIV2 2MCLK 0 1 2 3 4 5 sames PCM FRAME SYNCHRONIZATION SIGNALS PCM_OUT TIME-SLOT 31 8kFS PCMFSC CLKIN 0 1 2 3 4 5 6 CLKDIV2 2MCLK PCM_OUT 7 6 8kFS PCMFSC DR-00750 Internal Sync.) CLKIN CLKDIV2 6 TIME-SLOT 0 TIME-SLOT 0 TIME-SLOT 31 7 0 1 2 3 4 5 0 0 3 4 5 2 2 7 6 7 7 4 1 6 7 0 1 6 0 3 5 2MCLK 0 1 2 3 4 5 Figure 6 - TIMING DIAGRAMS (CLK_SEL = 1, CLKIN = 2MHz, EXTERNAL SYNC.) PCM OUTPUT STRUCTURE 6 7 0 2 1 4 3 6 5 0 7 6 3 5 4 2 1 0 7 6 TIME-SLOT 31 TIME-SLOT 0 sames PCM FRAME SYNCHRONIZATION SIGNALS PCM_OUT TIME-SLOT 31 8kFS PCMFSC CLKIN 0 1 2 3 4 5 CLKDIV2 2MCLK PCM_OUT 7 8kFS PCMFSC DR-00750 SA9401 15 SA9401 Disclaimer: The information contained in this document is confidential and proprietary to South African MicroElectronic Systems (Pty) Ltd ("SAMES") and may not be copied or disclosed to a third party, in whole or in part, without the express written consent of SAMES. The information contained herein is current as of the date of publication; however, delivery of this document shall not under any circumstances create any implication that the information contained herein is correct as of any time subsequent to such date. SAMES does not undertake to inform any recipient of this document of any changes in the information contained herein, and SAMES expressly reserves the right to make changes in such information, without notification,even if such changes would render information contained herein inaccurate or incomplete. SAMES makes no representation or warranty that any circuit designed by reference to the information contained herein, will function without errors and as intended by the designer. Any sales or technical questions may be posted to our e-mail adress below: energy@sames.co.za For the latest updates on datasheets, please visit our web site: http://www.sames.co.za South African Micro-Electronic Systems (Pty) Ltd P O Box 15888, 33 Eland Street, Lynn East, Koedoespoort Industrial Area, 0039 Pretoria, Republic of South Africa, Republic of South Africa Tel: Fax: 16 012 333-6021 012 333-8071 sames Tel: Fax: Int +27 12 333-6021 Int +27 12 333-8071 |
Price & Availability of SA9401
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |